The invention relates to the field of switching electrical power converters. More particularly, the invention relates to the field of pulse width modulating forward converters and post regulators.
FIG. 1 illustrates a schematic block diagram of a conventional pulse width modulating (PWM) forward converter. As illustrated in FIG. 1, a voltage source VS is coupled to a first terminal of a primary winding of a transformer T. A second terminal of the primary winding of the transformer T is coupled to a drain of a MOS transistor M. A source of the transistor M is coupled to a first terminal of a resistor RSENSE. A second terminal of the resistor RSENSE is coupled to a first ground node. A voltage signal ISENSE formed at the first terminal of the resistor RSENSE is representative of a level of current passing through the primary winding of the transformer T when the transistor M is active.
A first terminal of a secondary winding of the transformer T is coupled to an anode of a diode D. A cathode of the diode D is coupled to a first terminal of a capacitor C1, to an output node, and to a first terminal of a resistor R1. A second terminal of the secondary winding of the transformer T and a second terminal of the capacitor C1 are coupled to a second ground node. A second terminal of the resistor R1 is coupled to a first terminal of a resistor R2 and to an inverting input of an error amplifier A. A second terminal of the resistor R2 is coupled to the second ground node. The resistors R1 and R2 form a resistive divider for supplying the amplifier A with a signal which is proportional to an output voltage VOUT at the output node. The amplifier A can include optical elements so as to optically isolate the first ground node from the second ground node.
A non-inverting input of the amplifier A is coupled to a reference voltage VREF. The reference voltage VREF is representative of a desired level for the output voltage VOUT. An output of the amplifier A forms an error signal VEA and is coupled to a non-inverting input of a comparator CMP1. The error signal VEA is representative of a difference between the output voltage VOUT and a desired level for the output voltage. The first terminal of the resistor RSENSE is coupled to an inverting input of the comparator CMP1 and to an inverting input of a comparator CMP2. An output of the comparator CMP1 is coupled to a first input of a logic NAND gate U1. A current source is coupled to a first terminal of a capacitor C2 and to a non-inverting input of the comparator CMP2. A second terminal of the capacitor C2 is coupled to the first ground node. A voltage signal VSTART is formed at the first terminal of the capacitor C2.
An output of the comparator CMP2 is coupled to a second input of the NAND gate U1. An output of the NAND gate U1 is coupled to a set input S of a flip-flop U2. A reset input R of the flip-flop U2 is coupled to receive a clock signal VCLK. An inverted output {overscore (Q)} of the flip-flop U2 is coupled to a gate of the transistor M.
When the transistor M is active (turned on), current flows from the source VS and through the primary winding of the transformer T. This stores energy as an electromagnetic field associated with the primary winding of the transformer T. When the transistor M is inactive (turned off), the electromagnetic field collapses. By turning the transistor M on and off, energy is transferred to the secondary winding of the transformer T which induces a current to flow in the secondary winding. The current in the secondary winding of the transformer T is rectified by the diode D so as to form a voltage across the capacitor C1. A duty cycle utilized for operating the transistor M controls the level of the output voltage VOUT formed at the output node.
FIGS. 2a-b illustrate timing diagrams for the signals VEA, ISENSE and VCLK of the PWM forward converter illustrated in FIG. 1. When the clock signal VCLK transitions from a logical low voltage to a logical high voltage, the output {overscore (Q)} of the flip-flop U2 transitions to a logic high voltage. This turns on the transistor M. Under these conditions, current flows through the transistor M and the resistor RSENSE, as illustrated in FIG. 2a by the signal ISENSE ramping up. When the signal ISENSE reaches the level of the error signal VEA, this causes the output of the comparator CMP1 to change from a logic high voltage to a logic low voltage. As a result, the output of the NAND gate U1 changes from a logic low voltage to a logic high voltage and the output {overscore (Q)} of the flip-flop U2 transitions from. a logic high voltage to a logic low voltage. This turns off the transistor M. Upon a next transition of the clock signal VCLK, this cycle repeats. Note that as the error signal VEA increases, the transistor M stays on for a longer portion of each cycle of the clock signal VCLK because more time is required for the signal ISENSE to exceed the error signal VEA. Conversely, as the error signal VEA falls, the transistor M stays on a smaller portion of each cycle of the clock signal VCLK because less time is required for the error signal ISENSE to exceed the error signal VEA. Accordingly, the output voltage at the node VOUT is regulated to the desired level by adjusting the duty cycle of the transistor M according to requirements of a load (not shown) which can be coupled to the output node to receive the output voltage VOUT.
Under normal operating conditions, the voltage VSTART is at a higher level than the error signal VEA. Accordingly, the output of the comparator CMP2 is a logic high voltage when the output of the comparator CMP1 changes. Therefore, under normal operating conditions, the output of the comparator CMP2 does not affect the duty cycle of the transistor M and the PWM converter operates as described above.
Upon start up, however, the output voltage VOUT is low. As a result, the error signal VEA is relatively large. In absence of soft-start circuit elements, including the current source I, the capacitor C2 and the comparator CMP2, this large error signal would result in the transistor M being held on for a large portion of each cycle of the clock signal VCLK while the forward converter attempted to rapidly increase the output voltage to the desired level. As a result, excessive current would flow through the transistor M which would tend to cause premature failure of the transistor M.
Instead, upon start up, the current source I is turned on and the signal VSTART slowly ramps up. Before the level of the signal VSTART exceeds the level of the signal VEA, the duty cycle of the transistor M is not influenced by the signal VEA, but by the signal VSTART. As a result, the duty cycle of the transistor M gradually increases until the level of the signal VSTART exceeds the level of the error signal VEA.
While the soft-start circuit elements of FIG. 1 provide a useful function, they also result in a disadvantage, especially when elements of the forward converter are incorporated into an integrated circuit. More particularly, so that the signal VSTART ramps up slowly, the current produced by the current source I must be small in relation to the size of the capacitor C2. This constraint either requires that the capacitor C2 be external to the integrated circuit, which increases the pin count of the integrated circuit and, thus, the cost of producing the integrated circuit, or requires that the current produced by the current source I be so small as to be easily overwhelmed by noise and other transient signals, which reduces reliability.
Therefore, what is needed is improved soft-start technique for a PWM power converter.
Further, prior integrated circuits for controlling PWM power converters have been specifically tailored to the intended application. For example, a different integrated circuit design is utilized for a PWM forward converter than is utilized for a PWM post-regulator.
This requirement of multiple integrated circuit designs tends to increase the costs associated with each.
Therefore, what is needed is a universal integrated circuit for controlling a PWM power converter.
The invention is a universal controller for a pulse width modulating (PWM) power converter. The controller monitors an output voltage of the power converter and a current through a magnetic element of the power converter for modulating a duty cycle of a main power switch of the power converter. The main power switch is closed in response to a transition in a clock signal. When the main power switch is closed, the current through the magnetic element forms a sensing signal (current ramp) representative of the current through the main power switch. The sensing signal is compared to an error signal representative of a difference between the output voltage and a desired level for the output voltage. When the It sensing signal exceeds the error signal, the main power switch is opened. Opening and closing of the main power switch draws power from an input voltage source for forming the output voltage. In this manner, the duty cycle of the main power switch is controlled in a feedback loop. In a preferred embodiment, the controller is implemented as an eight pin mintegrated circuit.
According to an aspect of the present invention, the controller can be utilized for a power converter which is either a PWM forward converter or a PWM post regulator where differences between the PWM forward converter and the PWM post regulator are exclusively in circuitry external to the controller. In particular, the magnetic element of the power converter is a transformer, the main power switch for the PWM forward converter controls a current through a primary side of the transformer, whereas, the main power switch for the PWM post regulator controls a current through the secondary side of the transformer. When the power converter is a PWM forward converter, the sensing signal is positive in polarity, whereas, when the power converter is a PWM post regulator, the sensing signal is negative is polarity. A current sense circuit included in the controller forms a signal which is representative of the absolute value of the sensing signal for comparison to the error signal.
According to another aspect of the present invention, the controller includes a soft-start circuit which gradually increases a duty cycle of the main power switch upon start-up of the power converter. The soft-start circuit monitors the ramping up of a VCC power supply and, in response, forms a start-up voltage ramp. The start-up voltage ramp begins ramping when the VCC power supply reaches a first predetermined voltage level and is substantially proportional to a level of the VCC power supply as the level of VCC exceeds the first predetermined voltage level. In a preferred embodiment, the start-up voltage ramp is formed by generating a current which is substantially proportional to the level of the VCC supply (minus the first predetermined voltage level) and by applying this current to a resistor, such that the start-up voltage ramp is formed across the resistor. During start-up, the start-up voltage ramp is compared to the current ramp for controlling the duty cycle of the main power switch. As a result, the duty cycle gradually increases upon start-up as the level of the voltage supply increases. Unlike prior arrangements, the start-up circuit does not require an external capacitor for forming the start-up voltage ramp. This reduces the number pins required when the controller as implemented as an integrated circuit.
According to a further aspect of the present invention, a pulse skipping circuit disables switching of the main power switch when a load powered by the power converter draws a low level of current. When the output voltage rises, as tends to occur when the load draws a low level of current, the error signal decreases. The error signal is compared to a pulse skip reference voltage. When the level of the error signal falls below the level of the pulse skip reference voltage, then the main power switch is disabled until the error signal rises again. Preferably, the pulse skip reference voltage is inversely related to the supply voltage VCC. Accordingly, when the supply voltage VCC is at a higher level, the output voltage must rise to a higher level before the main power switch is disabled than when the supply voltage VCC is at a lower level. Therefore, forming the pulse skip reference voltage such that it is inversely related to the supply voltage tends to aid in spreading out in time pulsing of the main power switch under light load conditions. This tends to reduce switching noise while increasing efficiency.
According to yet another aspect of the present invention, the clock signal which is utilized to control switching of the main power switch can be selectively generated internally to the integrated circuit or externally to the integrated circuit. It is expected that when the power converter is a PWM forward converter, the clock signal is internally generated, whereas, when the power converter is a PWM post regulator, the clock signal is externally generated for synchronizing switching of the PWM post regulator with that of a pre-regulator.